#makefile支持编写变量，最好不要有空格
#加上@就不会回显了
cc=gcc
src=code.c
target=mybin
$(target):$(src)
	$(cc) $(src) -o $(target)
.PHONY:clean
clean:
	rm $(target)

#exe:code.c
#	@echo "编译....."
#	@gcc code.c -o exe
#.PHONY:clean
#clean:
#	@echo "清理....."
#	@rm -rf exe
